• 专利附录
  • 专利说明
  • 权利要求
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    • 专利摘要:
    First, the lower layer of chromium and the conductive layer of aluminum alloy are sequentially stacked and patterned to form a horizontal gate line including a gate line, a gate electrode, and a gate pad on the substrate. Next, a gate insulating film is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed thereon. Subsequently, a conductive layer including a lower layer of chromium and an upper layer of an aluminum alloy is stacked and patterned to form a data line including a data line crossing the gate line, a drain electrode having a source electrode, a protrusion or a branch, and a data pad. The protective film is then stacked and patterned to form contact holes exposing the drain electrode, gate pad, and data pad. In this case, at least a portion of the boundary of the contact hole exposing the drain electrode is formed to be located above the branch or the protrusion of the drain electrode. Of course, the gate pad and the data pad may also be formed to have branches or protrusions, and the boundary of the contact holes that expose them may also be formed to pass over the top of the branches or protrusions. Next, the IZO is stacked and patterned to form pixel electrodes, auxiliary gate pads, and auxiliary data pads connected to the drain electrodes, the gate pads, and the data pads through sidewalls and top surfaces thereof.
    公开号:KR20030044217A
    申请号:KR1020010074897
    申请日:2001-11-29
    公开日:2003-06-09
    发明作者:전상익
    申请人:삼성전자주식회사；
    IPC主号:
    专利说明:

    A contact structure of a wiring and a thin film transistor substrate including the same {A CONTACT STRUCTURE OF A WIRES, AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT STRUCTURE}
    [20] The present invention relates to a contact structure of a wiring, a method of manufacturing the same, a thin film transistor substrate including the same, and a method of manufacturing the same.
    [21] In general, the wiring in the semiconductor device is used as a means for transmitting a signal, it is required to minimize the signal delay.
    [22] In this case, in order to prevent signal delay, the wiring is generally made of a metal material having a low resistance, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy). However, since the wiring of aluminum or aluminum alloy has a weak physical or chemical property, corrosion occurs when the contact portion is connected to another conductive material, thereby deteriorating the characteristics of the semiconductor device. In particular, when the pixel electrode is formed using indium tin oxide (ITO), which is a transparent conductive material, as in a liquid crystal display device, the wiring of aluminum or an aluminum alloy is corroded at the contact portion that contacts the wiring of the ITO and aluminum or an aluminum alloy. This happens. In order to solve this problem, a technique of forming a pixel electrode using IZO, which does not cause corrosion even when contacted with aluminum-based wiring instead of ITO, has been developed.However, in the case of using IZO, there is a problem of increasing contact resistance at the contact portion. have.
    [23] An object of the present invention is to provide a contact structure of a wiring made of a low resistance material and at the same time having a low resistance contact characteristic.
    [24] Another object of the present invention is to provide a thin film transistor substrate including a contact structure of a wiring having excellent contact characteristics.
    [1] 1A and 3H are diagrams showing a contact structure of a wiring in an embodiment of the present invention,
    [2] 4 is a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention;
    [3] FIG. 5 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 4 taken along the line IV-IV.
    [4] 6A, 7A, 8A, and 9A are layout views of thin film transistor substrates illustrating an intermediate process of manufacturing a thin film transistor substrate for a liquid crystal display device according to a first embodiment of the present invention, in the order of their processes;
    [5] 6B is a cross-sectional view taken along the line VIb-VIb ′ in FIG. 6A;
    [6] FIG. 7B is a cross-sectional view taken along the line VIIb-VIIb ′ in FIG. 7A and illustrating the next step in FIG. 6B;
    [7] FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ in FIG. 8A and is a cross-sectional view showing the next step in FIG. 7B;
    [8] FIG. 9B is a cross-sectional view taken along the line IXb-IXb 'of FIG. 9A and illustrates the next step of FIG. 8B;
    [9] FIG. 10 is a table illustrating a result obtained by measuring contact resistance of a test pattern formed in a peripheral region of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.
    [10] 11 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.
    [11] 12 and 13 are cross-sectional views of the thin film transistor substrate illustrated in FIG. 11 taken along lines XII-XII 'and XIII-XIII',
    [12] 14A is a layout view of a thin film transistor substrate at a first stage of manufacture in accordance with a second embodiment of the present invention;
    [13] 14B and 14C are cross-sectional views taken along the lines XIVb-XIVb ′ and XIVc-XIVc ′ in FIG. 14A, respectively.
    [14] 15A and 15B are cross-sectional views taken along the lines XIVb-XIVb 'and XIVc-XIVc' in FIG. 14A, respectively, and are cross-sectional views taken in the next steps of FIGS. 14B and 14C,
    [15] FIG. 16A is a layout view of a thin film transistor substrate in the next steps of FIGS. 15A and 15B;
    [16] 16B and 16C are cross-sectional views taken along lines XVIb-XVIb 'and XVIc-XVIc', respectively, of FIG. 16A.
    [17] 17A, 18A, 19A and 17B, 18B, and 19B are cross-sectional views taken along the lines XVIb-XVIb 'and XVIc-XVIc' in FIG. 16A, respectively, illustrating the following steps in the order of the process. ,
    [18] 20A is a layout view of a thin film transistor substrate at a next stage of FIGS. 19A and 19B,
    [19] 20B and 20C are cross-sectional views taken along the lines XXb-XXb 'and XXc-XXc' of FIG. 20A, respectively.
    [25] In order to solve this problem, in the present invention, the wiring is formed to include a conductive film having a low contact resistance with IZO, and the sidewall of the conductive film is exposed through the contact hole at the contact portion, or an opening is formed in one of the double layers so that the other Reveal the curtain. At this time, the wiring is formed to have a protrusion or branch to maximize the area in contact with the IZO and the boundary line of the contact hole is to be located on the upper portion of the at least one branch or protrusion.
    [26] More specifically, in the contact structure of the wiring according to the present invention, the wiring formed on the substrate has a branch or a protrusion, and has a contact hole that exposes the insulating film covering the wiring, and the boundary of the contact hole that exposes the wiring is a wiring. While located outside the boundary of the contact portion, a portion of the boundary of the contact hole is located on top of at least one branch or protrusion of the wiring. An upper portion of the insulating film is made of IZO, and a conductive layer in contact with the wiring is formed through a contact hole.
    [27] Here, the wiring includes a lower layer made of chromium or molybdenum or molybdenum alloy and an aluminum or aluminum alloy and an upper layer formed inside the boundary line of the lower layer.
    [28] In the thin film transistor substrate including the contact structure according to the present invention, a gate line including a gate line extending in a horizontal direction on the insulating substrate and a gate electrode connected to the gate line is formed. A semiconductor layer is formed on an upper portion of the gate insulating layer covering the gate wiring, and a data line extending in the vertical direction crossing the gate line, a source electrode connected to the data line, and a source electrode separated from the source electrode and separated from the source electrode. A data line is formed that includes a drain electrode that faces the branch and has a branch or a protrusion. The passivation layer covering the data line and the semiconductor layer has a first contact hole exposing the boundary line of the drain electrode, and the boundary line passes over the at least one branch or protrusion. A pixel electrode connected to the drain electrode through the first contact hole is formed on the passivation layer.
    [29] The gate wiring or the data wiring is formed inside the lower layer of the chromium or molybdenum or molybdenum alloy and the boundary of the lower layer, and preferably includes the upper layer of aluminum or aluminum alloy.
    [30] The gate insulating layer and the passivation layer may be made of silicon nitride or an organic insulating material, and the pixel electrode may be made of IZO.
    [31] The gate wiring receives a scan signal from the outside and transfers the scan signal to the gate line, and includes a gate pad having a branch or a protrusion, and the data wiring transfers a data pad to a data line to receive an image signal from the outside and has a branch or protrusion. Wherein the passivation layer has a second contact hole exposing the gate pad or the data pad, and a boundary line of the second contact hole is located above the at least one branch or protrusion.
    [32] Here, sidewalls of the drain electrode and the data pad or the gate pad are exposed in the first or second contact hole, and the pixel electrode and the auxiliary data pad or the auxiliary data pad are in contact with at least the drain electrode and the sidewall of the data pad or the gate pad.
    [33] In addition, the data lines of the semiconductor layer except for the channel portion between the source and drain electrodes may have the same shape.
    [34] Then, the contact structure of the wiring according to the embodiment of the present invention and the thin film transistor substrate including the same will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice. do.
    [35] 1A and 3H illustrate wiring and contact holes in an embodiment of the invention.
    [36] As a semiconductor device, especially a wiring for transmitting a signal, a metal material of aluminum or aluminum alloy having a low resistivity of 15 μΩcm or less is suitable to minimize signal delay. In this case, the wiring should be connected to another conductive layer in order to receive a signal from the outside or to transmit a signal to the outside, and the contact resistance at the contact portion should be small when contacting the other conductive material in the manufacturing process. To this end, in the method for manufacturing a contact structure of a wire according to an embodiment of the present invention, as shown in FIGS. 1A and 1B, a conductive material having a low contact resistance with IZO, such as molybdenum, molybdenum alloy, chromium, or the like, is formed on the substrate 10. The first conductive layer 11 including the lower layer 111 and the upper layer 112 made of aluminum or an aluminum alloy having low resistance is stacked and patterned to form the wiring 11 to cover the wiring 11. The insulating film 12 is laminated. In this case, the wiring 11 may be formed in a tapered structure such that a part of the sidewall of the lower layer 111 is exposed from the upper layer 112. Subsequently, the insulating film 12 is patterned to form a contact hole 13 exposing the wiring 11, and the upper portion of the insulating film 12 is directly connected to the wiring 11 through the contact hole 13 and made of IZO. 2 conductive layer 14 is formed. At this time, the contact hole 13 of the insulating film 12 is formed so that the side wall boundary surface of the wiring 11, in particular, the side wall boundary surface of the lower film 111 is sufficiently exposed, so that the IZO film 14 and the lower film 111 are sufficiently in contact with each other. To form a contact. Here, the second conductive layer 14 connected to the wiring 11 through the contact hole 13 is disconnected due to the step of the contact hole 13 or the under-cut under the wiring 11. It is preferable to form the contact hole 13 so that the distance d between the boundary line of the wiring 11 exposed from the contact hole 13 and the boundary line of the contact hole 13 adjacent to the contact hole 13 does not deviate from the range of 2 μm so as to prevent it. Do. Here, although the wiring 11 is formed in a tapered structure so that the lower layer 111 is exposed when the wiring 11 is formed, the contact hole exposing the wiring 11 even if the wiring 11 does not have a tapered structure ( When forming the 13, the lower layer 111 of the wiring 11 may be exposed.
    [37] In addition, in the contact structure of the wiring and the manufacturing method thereof according to another embodiment of the present invention, as shown in FIGS. 2A and 2B, at least one or more openings may be formed in the upper layer 112 of the wiring 11 of the first conductive layer. 15 is formed, and the insulating film 12 covering the wiring 11 is patterned to expose the opening 15 to form the contact hole 13. Next, the second conductive layer 14 in contact with the lower layer 111 of the wiring 11 is formed in the opening 15. In this case, the opening 15 is preferably formed to have an area of 4 × 4 μm or less. If the opening 15 is made smaller, only one mask may be used to form the upper layer 112 and the lower layer 111. have. That is, when patterning the upper layer 112 and the lower layer 111 having different shapes, first, the upper layer 112 is formed using the photoresist pattern as an etching mask in a photolithography process. Subsequently, the lower layer 111 is etched using the remaining photoresist pattern or the upper layer 112 as an etching mask. At this time, since the opening 15 is very small with an area of 4 × 4 μm or less, since the etching process is very slow in the opening 15, the lower layer 111 remains without being completely removed. In this case, the upper layer 112 and the lower layer 111 having different shapes may be formed by a photolithography process using one photoresist layer pattern.
    [38] On the other hand, as shown in FIGS. 3A to 3D, the margin of misalignment between the wiring 11 and the contact hole 13 is set while at least a portion of the boundary line of the wiring 11 is located inside the boundary line of the contact hole 13. The wiring 11 or the contact hole 13 may have various shapes so as to have a shape, and as shown in FIG. 3E, a plurality of openings 15 exposing the wiring 11 may be formed.
    [39] 1A and 1B have a disadvantage in that it is difficult to secure a contact area between the lower layer 111 of the wiring 11 as the first conductive layer and the second conductive layer 14. When applying such a structure as a pad in a thin film transistor substrate for a liquid crystal display device, the pad and the output terminal of the driving integrated circuit are connected through conductive particles of an anisotropic conductive film, the wiring 11 being the first conductive layer. When the contact area between the lower layer 111 and the second conductive layer 14 is small, the contact area between the conductive particles and the second conductive layer 14 also becomes difficult to secure, and the contact resistance of the contact portion also increases. . In order to solve this problem, the contact area between the lower layer 111 of the wiring 11, which is the first conductive layer, and the second conductive layer 14 should be secured. For this purpose, as shown in FIG. The wiring 11 is formed to have protrusions or branches. At this time, it is very difficult to form the distance d between the boundary line of the wiring 11 exposed from the contact hole 13 and the boundary line of the contact hole 13 adjacent thereto during the manufacturing process within a range of 2 μm. The gap d may be formed nonuniformly. In order to solve this problem, it is preferable to form the distance d between the boundary line of the wiring 11 exposed from the contact hole 13 and the boundary line of the adjacent contact hole 13 in the manufacturing process in a range of 2 μm or more. However, in this case, the second conductive layer 14 (see FIG. 1B) may be disconnected due to the step difference between the insulating layer 12 (see FIG. 1B). As shown in FIGS. 3G and 3H, to solve this problem, The wiring 11 is formed to have branches or protrusions, and at least one branch of the wiring 11 is formed to extend out of the boundary of the contact hole 13.
    [40] Such a contact structure of wirings and a method of manufacturing the same can also be applied to a thin film transistor for a liquid crystal display device and a method of manufacturing the same.
    [41] Next, a thin film transistor substrate for a liquid crystal display and a manufacturing method including the contact structure of the wiring according to the present invention will be described in detail with reference to the accompanying drawings.
    [42] First, the structure of the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5.
    [43] 4 is a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the thin film transistor substrate shown in FIG. 4 taken along the line V-V ′.
    [44] A gate wiring made of a metal material of aluminum or aluminum alloy having low resistance is formed on the insulating substrate 10. The gate wire is connected to the gate line 22 and the gate line 22 extending in the horizontal direction, and are connected to the gate pad 24 and the gate line 22 which receive a gate signal from the outside and transmit the gate signal to the gate line. A gate electrode 26 of the thin film transistor.
    [45] On the substrate 10, a gate insulating film 30 made of silicon nitride (SiN x ) covers the gate wirings 22, 24, and 26.
    [46] A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24 in an island shape, and silicide or n-type impurities are doped with high concentration on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as n + hydrogenated amorphous silicon are formed, respectively.
    [47] On the resistive contact layers 55 and 56 and the gate insulating layer 30, aluminum (Al) or aluminum alloy (Al alloy), molybdenum (Mo) or molybdenum-tungsten (MoW) alloy, chromium (Cr), tantalum (Ta), Data lines 62, 64, 65, 66, and 68 are formed of a lower film 601 and an upper film 602, such as titanium (Ti). The data line is formed in the vertical direction and crosses the gate line 22 to define a pixel, the data line 62 and the branch of the data line 62 and the source electrode 65 extending to the upper portion of the ohmic contact layer 54. ), Which is connected to one end of the data line 62 and is separated from the data pad 68 and the source electrode 65 to which an image signal from the outside is applied, and is opposite to the source electrode 65 with respect to the gate electrode 26. And a drain electrode 66 formed on the ohmic contact layer 56 and a conductive pattern 64 for a storage capacitor that overlaps the protruding gate line 22. At this time, the conductive pattern 64 for the storage capacitor, the drain electrode 66 and the data pad 68 have branches or protrusions, as shown in FIGS. 3F to 3H, and the lower layer exposed from the upper layer 602 through this. The side area of 601 can be secured widely.
    [48] The data lines 62, 65, 66, 68 are preferably formed of a single film of aluminum or aluminum alloy, but may be formed of two or more layers. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having a low contact resistance with other materials, especially IZO. Examples include Al (or Al alloys) / Cr or Al (or Al alloys) / Mo (or Mo alloys), and the like. In an embodiment of the present invention, the data wires 62, 65, 66, and 68 are made of chromium. The double film of the lower film 601 and the upper film 602 of aluminum-neodymium alloy.
    [49] A passivation film 70 made of silicon nitride is formed on the data lines 62, 64, 65, 66, and 68 and the semiconductor layer 40 which is not covered.
    [50] In the passivation layer 70, contact holes 72, 76, and 78 that expose the conductive pattern 64 for the storage capacitor, the drain electrode 66, and the data pad 68, respectively, are formed, and together with the gate insulating layer 30. The contact hole 74 which exposes the gate pad 24 is formed. Here, the contact holes 72, 76, and 78 are formed so that the boundary lines of the conductive capacitor pattern 64 for the storage capacitor 64, the drain electrode 66, and the data pad 68 are exposed. 64, sidewalls of the lower layer 601 and the upper layer 602 of the drain electrode 68 and the data pad 68 are exposed through the contact holes 72, 76, and 78. Here, most of the boundary of the conductive pattern conductor 64, the drain electrode 66, and the data pad 68 for the storage capacitor is formed inside the boundary of the contact holes 72, 76, 78, but these (64, 66, 68) At least one of the branches or protrusions of is extended out of the boundary line of the contact holes 72, 76, 78 to the bottom of the protective film 70. In addition, the boundary line of the contact hole 72 positioned above the gate line 22 should be positioned inside the boundary line of the conductive pattern conductor 64 for the storage capacitor, which will be described in detail in the manufacturing process. In such a structure, the conductive pattern 64 for the storage capacitor, the drain electrode 66 and the data pad 68 have branches or protrusions, and the lower film exposed from the upper film 602 of these 64, 66, 68. Since the side area of 601 can be secured widely, the area of the underlayer 601 exposed through the contact holes 72, 76, and 78 can be maximized.
    [51] On the passivation layer 70, a pixel electrode 82, which is electrically connected to the drain electrode 66 and the storage capacitor 64 and positioned in the pixel, is formed through the contact hole 76. At this time, the conductive capacitor pattern 64, the drain electrode 66, and the data pad 68 for the storage capacitor have branches or protrusions, and the pixel electrode 82 has a conductive capacitor conduction exposed from the contact holes 72 and 76. The sidewalls of the sieve pattern 64 and the drain electrode 66, in particular, the sidewalls of the lower film 601 of these 64 and 66 are in contact with a large enough area. In addition, the auxiliary gate pad 84 and the auxiliary data pad 88, which are connected to the gate pad 24 and the data pad 68, respectively, are formed on the passivation layer 70 through the contact holes 74 and 78. At this time, the data pad 68 also has branches or protrusions, so that the lower layer 601 is in contact with the auxiliary data pad 88 in a large area. Therefore, the contact resistance between the pixel electrode 88 and the drain electrode 44 or the conductive pattern 64 for the storage capacitor can be minimized. The pixel electrode 82, the auxiliary gates, and the data pads 84 and 88 are made of indium zinc oxide (IZO). In addition, the conductive pattern 64 for the storage capacitor, the drain electrode 66 and the data pad 68 have branches or protrusions formed to the lower portion of the passivation layer 70 so that the pixel electrode 82 and the auxiliary data pad 88 are formed. A part of is in contact with the drain electrodes 66 and the upper portion of the data pad 68, 66, 68, the pixel electrode 82 at the boundary of the contact holes 72, 26 due to the step of the protective film 70 ) And the auxiliary data pad 88 can be prevented from being disconnected.
    [52] 1 and 2, the pixel electrode 82 is overlapped with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.
    [53] Next, a method of manufacturing the thin film transistor substrate for a liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5 and FIGS. 6A to 9B.
    [54] First, as shown in FIGS. 6A and 6B, on the substrate 10, about 2,500 mW using a target containing Al-Nd containing 2 at% of Nd, among the metals of aluminum or aluminum alloy having low resistance. Sputtering is sputtered and patterned at about 150 ° C. to form a horizontal gate wiring including a gate line 22, a gate electrode 26, and a gate pad 24, and having a tapered structure.
    [55] Next, as shown in FIGS. 7A and 7B, a three-layer film of a gate insulating film 30 made of silicon nitride, a semiconductor layer 40 made of amorphous silicon, and a doped amorphous silicon layer 50 is successively stacked, and a mask is formed. The semiconductor layer 40 and the ohmic contact layer 50 are formed on the gate insulating layer 30 facing the gate electrode 24 by patterning the semiconductor layer 40 and the doped amorphous silicon layer 50 by the patterning process. do. Here, the gate insulating film 30 is preferably formed by laminating silicon nitride to a thickness of about 2,000 to 5,000 Pa, in a temperature range of 250 to 400 ° C.
    [56] Next, as shown in FIGS. 8A to 8B, the lower film 601 made of molybdenum, molybdenum alloy, chromium, or the like is about 500 kPa and has a thickness of about 2 at% of the metal of aluminum or aluminum alloy having low resistance. The upper layer 602 was sequentially laminated by sputtering at a temperature of about 150 ° C. to about 2,500 mm using a target of Al-Nd alloy including Nd, and then patterned by a photo process using a mask to form a gate line. A data line 62 intersecting with the 22, a source electrode 65 connected to the data line 62 and extending to an upper portion of the gate electrode 26, and a data pad 62 connected to one end thereof. 68, the conductive pattern 64 for the storage capacitor which is separated from the source electrode 64 and overlaps the drain electrode 66 and the gate line 22 facing the source electrode 65 around the gate electrode 26. ) And tapered structure Losing data forms a wiring. Here, both the upper layer 602 and the lower layer 601 may be etched by wet etching, the upper layer 602 may be etched by wet etching, and the lower layer 601 may be etched by dry etching, and the lower layer 601 may be etched. ) Is a molybdenum or molybdenum alloy film may be patterned by one etching condition with the upper film 602. In addition, an opening may be formed only in the upper layer 602 of the drain electrode 66 to finally form a contact structure as shown in FIGS. 2A and 2B. It is preferable not to add a separate photo etching process using.
    [57] At this time, the lower layer 601 is prevented from being cut under the upper layer 602 so that the later formed IZO layer and the lower layer 601 are sufficiently in contact with each other, or the lower layer 601 is outside the upper layer 602. It is preferable to form so that it may come out. For this purpose, when the lower layer 601 is formed of molybdenum or molybdenum alloy, the ratio of the thicknesses of the lower layer 601 and the upper layer 602 is 1: 5 or more laminated, and the DIP mode is performed to optimize the battery reaction. Prevents the undercoat from being cut under. In addition, when the lower layer 601 is formed of chromium, a portion of the upper layer 602 of aluminum or an aluminum alloy may be removed in a process of laminating the lower layer 601 to a thickness of 500 kPa or less and removing the photoresist layer. Conditions are applied to form the lower layer 601 of chromium out of the upper layer 602. At this time, the conductive pattern 64 for the storage capacitor, the drain electrode 66, and the data pad 68 are formed to have protrusions or branches as shown in the drawing, so that the chromium or molybdenum or molybdenum alloy exposed from the upper film 602 is formed. By securing a wide area of the lower layer 601, the contact resistance between the lower layer 601 and the pixel electrode 82 and the auxiliary data pad 88 formed thereafter may be minimized, and the contact area may be maximized.
    [58] Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.
    [59] Next, as shown in FIGS. 9A and 9B, an inorganic insulating film such as silicon nitride is stacked in a range of 250 to 400 ° C. to form a protective film 70, and together with the gate insulating film 30 in a photolithography process using a mask. Patterning by dry etching forms contact holes 74, 76, 78 that expose the gate pad 24, the drain electrode 66, and the data pad 68, respectively. Here, the contact holes 72, 76, 78 are formed so that the boundary of the conductive pattern 64 for the storage capacitor, the drain electrode 66, and the data pad 68, especially the sidewalls of the lower layer 601, are exposed. At least one of the branches or protrusions of the conductive capacitor pattern 64, the drain electrode 66, and the data pad 68 for the storage capacitor is not completely exposed in the contact holes 72, 76, 78. In this case, a portion of the gate insulating layer 30 may be etched in the contact holes 72, 76, and 78 to expose the substrate 10. In this way, the pixel electrode 82 and the auxiliary data pad 88 and the conductive pattern 64 for the storage capacitor, the drain electrode 66, and the data pad 68 formed later in the contact holes 72, 76, and 78 are formed. ), The contact resistance between the lower film 601 and the IZO films 82 and 88 of those 64, 66 and 68 having excellent contact characteristics with each other can be minimized while maximizing the contact area. It is possible to prevent the disconnection of the pixel electrode 82 or the auxiliary data pad 88 at the boundary between the contact holes 72, 76, 78. Here, the boundary line of the contact hole 72 located above the gate line 22 is formed to be located inside the boundary line of the conductor pattern 64 for the storage capacitor. If the boundary line of the contact hole 72 located above the gate line 22 is located outside the boundary line of the conductive capacitor conductor pattern 64, the gate insulating film 30 is etched when the contact hole 72 is formed. As a result, the gate line 22 is exposed, which causes a problem in that the pixel electrode 82 and the gate line 22 formed later are short-circuited. At this time, in order to prevent the undercut from occurring in the contact portion and the boundary line of the contact holes 72, 76, 78 positioned outside the data pad 68, the conductive capacitor pattern 64 for the storage capacitor and the drain electrode 66 and The distance between the boundary lines of the data pad 68, the storage capacitor conductor pattern 64, and the drain electrode 66 adjacent thereto may be within 2 μm. That is, the boundaries of the contact holes 72, 78, and 76 located outside the data pad 68, the conductive capacitor pattern 64 for the storage capacitor, and the drain electrode 66, and the data pad 68 and the storage capacitor adjacent thereto. When the boundary between the entire pattern 64 and the drain electrode 66 is far apart, the gate insulating film 30 is excessively etched under the lower layer 601 to form the undercuts when the contact holes 72, 78, and 76 are formed. This happens. In this case, the pixel electrode 82 formed later may be disconnected from the lower portion of the drain electrode 66 due to the step difference in the gate insulating layer 30, thereby increasing the contact resistance of the contact portion. However, the boundaries of the contact holes 72, 78, and 76 located outside the data pad 68, the conductive capacitor pattern 64 for the storage capacitor, and the drain electrode 66, and the data pad 68 and the storage capacitor adjacent thereto. If the contact holes 72, 78, and 76 are formed such that the gap between the conductor pattern 64 and the drain electrode 66 is within 2 m, the gate insulating film 30 is excessively formed under the lower film 601. Without etching, the sidewall inclined surface of the data pad 68, the storage capacitor conductor pattern 64, and the drain electrode 66 can be completely exposed. Of course, the contact holes 74 exposing the pads 24 may also be formed such that the boundaries of the pads 24 are exposed.
    [60] Next, as shown in FIGS. 4 and 5, the IZO film is laminated by sputtering and patterned using a mask to conduct the drain electrode 66 and the conductor pattern 64 for the storage capacitor through the contact holes 72 and 76. ) And an auxiliary gate pad 84 and an auxiliary data pad 88 respectively connected to the gate pad 24 and the data pad 68 through the pixel electrode 82 and the contact holes 74 and 78 connected to each other. do. At this time, the pixel electrode 82 and the auxiliary data pad 88 are not disconnected because under cut does not occur under the drain electrode 66, the conductive pattern 64 for the storage capacitor, and the data pad 68. Contact with the lower layer 601 of the chromium having a low contact resistance with and can minimize the contact resistance of the contact portion. In the exemplary embodiment of the present invention, a target for forming the IZO films 82, 84, and 88 was a product called indium x-metal oxide (IDIXO) manufactured by idemitsu, and the target was In 2 O 3 and ZnO, and the content of Zn in In + Zn is preferably in the range of 15-20 at%. In addition, in order to minimize contact resistance, the IZO film is preferably laminated in the range of 250 ° C or lower.
    [61] In the manufacturing process according to the exemplary embodiment of the present invention, the contact structure was formed in a test pattern in the same manner as the structure formed in the pixel area in the peripheral area outside the display area, which is a set of pixels, and the contact resistance of the contact part was measured. For each case was measured. That is, in the first case in which the contact hole 76 is formed on the drain electrode 66, the test pattern includes a boundary line of the contact hole 76 located outside the drain electrode 66 and a boundary line of the drain electrode 66 adjacent thereto. In the second case in which the contact holes are largely formed such that the intervals are 3 µm or more, and as in the contact structure of the present invention, the boundary line of the contact hole 76 located outside the drain electrode 66 and the drain electrode 66 adjacent thereto are The test pattern was formed in the third case in which the interval between the boundary lines of the microcavity was within 2 μm, and the contact resistance was measured for 200 test patterns. As a result, the contact resistance was measured to be higher than E7Ω in the first and second cases, and the contact resistance was measured to be lower than E6Ω in the third case.
    [62] On the other hand, the contact resistance of the contact portion was measured through a test pattern for various process conditions in the manufacturing process.
    [63] FIG. 10 is a table illustrating a result of measuring contact resistance of a test pattern formed in a peripheral area of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.
    [64] At this time, the test pattern is formed in the periphery outside the display area, as shown in FIGS. 1A and 1B, a wiring consisting of a lower layer of chromium, which is a metal layer for data wiring, and an upper layer of an aluminum alloy, an insulating film made of silicon nitride, and an IZO film having contact holes. The contact resistance was measured by forming 200 contact portions by simplifying the structure of the three-layer film. Here, the first pattern is a case where the contact portion is formed so that the boundary line of the contact hole is located only on the upper portion of the wiring, and the second pattern is a case where the contact portion is formed such that the side wall inclined surface of the wiring is in contact with the IZO film as in the embodiment of the present invention. . The insulating film is laminated with different thicknesses of the protective film and the gate insulating film, respectively, at a thickness of 2,000 kPa and 3,000 kPa at temperatures of 235 ° C and 310 ° C, respectively, and the wirings are laminated with different aluminum alloy films at 150 ° C and 50 ° C, respectively. Each contact resistance was measured. In addition, when the wiring is exposed to the gas for etching the resistive contact layers of 1,500 Å and 3,000 와, and the contact hole is formed by etching the insulating film in the PE mode for 63 seconds and 68 seconds, and the ICP of 1,000 W and 400 W. The contact resistances were measured for the case where the insulating film was etched in the mode to form the contact holes, and the wirings exposed through the contact holes were not cleaned or cleaned for 70 seconds.
    [65] As shown in Table 10, the contact resistance of the first pattern was found to be large in the range of 5.3 MΩ to 4.0 GΩ when the contact hole was formed to 10 μm × 10 μm, and the contact resistance of the second pattern was in the range of 14 KΩ to 515 KΩ. It was measured well below E5Ω. Here, the contact resistance of the first pattern may be well measured to be 60 K . As a result of the detailed examination, the contact structure of the first pattern is formed such that the boundary line of the wiring is exposed in the contact hole like the contact structure of the second pattern. The structure has been sufficiently in contact with the sidewalls of the film and the wiring, especially the lower film.
    [66] In addition, in the case where the contact holes were formed to be 7 μm × 7 μm, the contact resistance of the first pattern was large in the range of 12 MΩ to 7.9 GΩ, and the contact resistance of the second pattern was in the range of 18 KΩ to 664 KΩ, well below E5Ω. Was measured. In addition, when the contact holes were formed in 4 μm × 4 μm, the contact resistance of the first pattern was large in the range of 48 MΩ to 85 GΩ, and the contact resistance of the second pattern was well measured in the range of 30 KΩ to 1.2 MΩ.
    [67] The structure of the thin film transistor array substrate according to the embodiment of the present invention includes a conductive film of aluminum or aluminum alloy in which the gate wirings 22, 24, 26 and the data wirings 62, 64, 66, and 68 have low resistance. At the same time, the contact resistance between the contact portion, in particular, the data wiring and the pixel electrode 82 of the IZO film can be minimized, so that it can be applied to a liquid crystal display device having a large screen.
    [68] As described above, the method can be applied to a manufacturing method using five masks, but the same method can be applied to a manufacturing method of a thin film transistor substrate for a liquid crystal display device using four masks. This will be described in detail with reference to the drawings.
    [69] First, the unit pixel structure of the thin film transistor substrate for a liquid crystal display device completed using the four masks according to the exemplary embodiment of the present invention will be described in detail with reference to FIGS. 11 to 13.
    [70] 11 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIGS. 12 and 13 are lines XII-XII 'and XIII-XIII', respectively, of the thin film transistor substrate shown in FIG. 8. A cross-sectional view taken along the line.
    [71] First, a gate wiring including a gate line 22, a gate pad 24, and a gate electrode 26 made of a low resistance conductive material of aluminum or an aluminum alloy is formed on the insulating substrate 10 as in the first embodiment. It is. The gate wiring includes a sustain electrode 28 that is parallel to the gate line 22 on the substrate 10 and receives a voltage such as a common electrode voltage input to the common electrode of the upper plate from the outside. Here, the gate pad 24 is formed to have a protrusion or a branch like the data pad 68 in the first embodiment. The storage electrode 28 overlaps with the conductive capacitor conductor 68 for the storage capacitor connected to the pixel electrode 82, which will be described later, to form a storage capacitor which improves the charge retention capability of the pixel. The pixel electrode 82 and the gate line, which will be described later, If the holding capacity generated by the overlap of (22) is sufficient, it may not be formed.
    [72] The gate wirings 22, 24, 26, and 28 may be formed of a single layer made of aluminum or an aluminum alloy, but the lower layer 201 made of chromium or molybdenum or molybdenum alloy or tantalum or titanium having a low contact resistance with IZO. And a top film 202 made of aluminum or an aluminum alloy.
    [73] A gate insulating film 30 made of silicon nitride (SiN x ) is formed on the gate wirings 22, 24, 26, and 28 to cover the gate wirings 22, 24, 26, and 28.
    [74] Semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed on the gate insulating layer 30, and high concentrations of n-type impurities such as phosphorus (P) are formed on the semiconductor patterns 42 and 48. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.
    [75] On the ohmic contact layer patterns 55, 56, and 58, a data line including a conductive film made of a conductive material of aluminum or an aluminum alloy having low resistance is formed. The data line is a thin film transistor which is a branch of the data line 62 formed in the vertical direction, the data pad 68 connected to one end of the data line 62 to receive an image signal from the outside, and the data line 62. And a data line portion of the source electrode 65 of the source electrode 65. The data line portion is separated from the data line portions 62, 68, and 65, and the source electrode 65 is separated from the gate electrode 26 or the channel portion C of the thin film transistor. It also includes a conductive capacitor conductor 64 for the storage capacitor located on the drain electrode 66 and the storage electrode 28 of the thin film transistor located on the opposite side. When the sustain electrode 28 is not formed, the conductor pattern 64 for the storage capacitor is also not formed. Here, as in the first embodiment, in order to maximize the area where the lower layer 601 is exposed and minimize the contact resistance of the contact portion, the conductive capacitor pattern 64, the drain electrode 66, and the data pad 68 for the storage capacitor are It has a protrusion or branch.
    [76] The data lines 62, 64, 65, 66, 68 may also be formed of a single layer made of a metal of aluminum or an aluminum alloy like the gate lines 22, 24, 26, 28, but the same as in the first embodiment. It is formed of a double film including a lower film 601 made of chromium or molybdenum or molybdenum alloy or tantalum or titanium and a top film 602 made of aluminum or aluminum alloy.
    [77] The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor pattern 64 for holding capacitors.
    [78] The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor pattern 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has data wiring and contact. Slightly different from the rest of the layer pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.
    [79] A passivation film 70 made of silicon nitride or an organic insulating material is formed on the data lines 62, 64, 65, 66, and 68.
    [80] The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the data pad 68, and the conductive pattern 64 for the storage capacitor, and also the gate along with the gate insulating film 30. It has a contact hole 74 which exposes the pad 24. At this time, as in the first embodiment, all of the contact holes 72, 74, 76, and 78 have sidewalls of the conductive pattern 64 for the storage capacitor, the gate pad 24, the drain electrode 66, and the data pad 68. In most cases, in particular, the lower layers 201 and 601 having low contact resistance with the IZO are formed to be exposed, and boundary lines of the contact holes 72, 74, 76, and 78 are positioned on at least one branch or protrusion.
    [81] On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. The pixel electrode 82 is also connected to the conductive capacitor pattern 64 for the storage capacitor through the contact hole 72 to transmit the image signal to the conductor pattern 64. On the other hand, an auxiliary gate pad 84 and an auxiliary data pad 88 connected to the gate pad 24 and the data pad 68 through the contact holes 74 and 78, respectively, are formed. 68) and to protect the pads and the adhesion of the external circuit device, and is not essential, their application is optional. Here too, at the contacts, the IZO films 82, 84, 88 have low contact resistance with the conductive patterns 64 for the storage capacitor, the gate pads 24, the drain electrodes 66, and the sidewalls of the data pads 68, in particular with the IZO. The branches are in contact with the underlayers 201 and 601.
    [82] Although the transparent IZO is mentioned as an example of the material of the pixel electrode 82, it may be formed of a transparent conductive polymer or the like. In the case of a reflective liquid crystal display, an opaque conductive material may be used.
    [83] Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having the structure of FIGS. 11 to 13 using four masks will be described in detail with reference to FIGS. 11 to 13 and 14A to 21C. .
    [84] First, as shown in FIGS. 14A to 14C, 2 at% of the lower layer 201 made of molybdenum, molybdenum alloy, chromium, etc. having a lower contact resistance with IZO than aluminum, and aluminum or aluminum alloy having low resistance, After stacking the upper layer 202 by sputtering using an Al-Nd alloy target including Nd, the gate line 22 on the substrate 10 by a photolithography process using a first mask, A gate wiring including the gate pad 24, the gate electrode 26, and the sustain electrode 28 is formed in a tapered structure. Here, the lower layer 201 is formed to come out of the upper layer 202 so that the IZO layer and the lower layer 201 formed thereafter are sufficiently in contact with each other, and the gate pad 24 is formed to have a branch or a protrusion. . To this end, when the lower layer 201 is formed of molybdenum or molybdenum alloy, the ratio of the thicknesses of the lower layer 201 and the upper layer 202 is 1: 5 or more, and the entire substrate is immersed in an etchant to perform etching. Etching is performed in DIP mode to optimize cell response to prevent under film from being cut. In addition, when the lower layer 201 is formed of chromium, a portion of the upper layer 202 of aluminum or an aluminum alloy may be removed in the process of laminating the lower layer 201 to a thickness of 500 GPa or less and removing the photosensitive layer. Conditions are applied to form the lower layer 201 of chromium out of the upper layer 202.
    [85] Next, as shown in FIGS. 15A and 15B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kPa to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. A conductor layer including a top film 601 made of aluminum or an aluminum alloy having a low resistance and a bottom film 601 made of chromium or molybdenum or molybdenum alloy. 60) is deposited to a thickness of 1,500 kPa to 3,000 kPa by sputtering or the like, and then the photosensitive film 110 is applied thereon to a thickness of 1 μm to 2 μm.
    [86] Thereafter, the photosensitive film 110 is irradiated with light through a second mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 16B and 16C. In this case, among the photoresist patterns 112 and 114, the channel portion C of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed, and all the photoresist of the other portion B is removed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable to make the thickness of the 1st part 114 into 1/2 or less of the thickness of the 2nd part 112, for example, it is good that it is 4,000 Pa or less.
    [87] As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the A region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.
    [88] In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.
    [89] When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all molecules are decomposed, so it should not be so.
    [90] The thin film 114 is formed by using a photoresist film made of a reflowable material, and is exposed to a conventional mask that is divided into a part that can completely transmit light and a part that cannot fully transmit light, and then develops and ripples. It can also be formed by letting a part of the photosensitive film flow to the part which does not remain by making it low.
    [91] Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the lower layer of the data line remain in the data wiring portion A, and only the semiconductor layer should remain in the channel portion C, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.
    [92] First, as shown in FIGS. 14A and 14B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, so that the photoresist patterns 112 and 114 may also be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.
    [93] When the conductor layer 60 includes one of Mo or MoW alloy, Al or Al alloy, and Ta, any of dry etching and wet etching can be used. However, since Cr is not easily removed by the dry etching method, it is preferable to use only wet etching if the conductor layer 60 is Cr. In the case of wet etching in which the conductor layer 60 is Cr, CeNHO 3 may be used as an etchant. In the case of dry etching in which the conductor layer 60 is Mo or MoW, the mixed gas or CF of CF 4 and HCl may be used as the etching gas. A mixed gas of 4 and O 2 can be used, and in the latter case, the etching ratio to the photoresist film is almost the same.
    [94] In this way, as shown in Figs. 17A and 17B, only the conductor layer of the channel portion C and the data wiring portion B, that is, the conductor pattern 67 for the source / drain and the conductor pattern 64 for the storage capacitor All of the conductor layer 60 of the remaining portion B is removed, revealing the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 have the same shape as the data wires 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. Here, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.
    [95] Subsequently, as shown in FIGS. 18A and 18B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF 6 and HCl or a mixed gas of SF 6 and O 2 , the two films can be etched to almost the same thickness. When the etching ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.
    [96] This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 18A and 18B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductor patterns 64, respectively.
    [97] Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.
    [98] Next, as illustrated in FIGS. 19A and 19B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under a condition in which the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in (). For example, those of etching the SF 6 and O 2 by using the mixed gas of the source / drain conductive pattern 67. In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include the aforementioned mixed gas of CF 4 and HCl or mixed gas of CF 4 and O 2 , and CF 4 and O Using 2 can leave the semiconductor pattern 42 in a uniform thickness. In this case, as shown in FIG. 19B, a part of the semiconductor pattern 42 may be removed to reduce the thickness, and the second part 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.
    [99] In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.
    [100] Of course, as shown in the figure, the lower layer 601 of the data lines 62, 64, 65, 66, 68, in particular, the drain electrode 66, the data pad 68, and the conductive pattern 64 for the storage capacitor are It is formed to have branches or protrusions to be exposed to a sufficiently large area.
    [101] Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be made after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.
    [102] As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.
    [103] After forming the data lines 62, 64, 65, 66, and 68 in this manner, as shown in FIGS. 20A and 20B, silicon nitride is deposited in the range of 250 to 400 ° C. by the CVD method or an acrylic type having excellent planarization characteristics. An organic insulating material is coated to form the protective film 70. Subsequently, the passivation layer 70 is etched together with the gate insulating layer 30 by using a third mask to form the drain electrode 66, the gate pad 24, the data pad 68, and the conductive pattern 64 for the storage capacitor. Contact holes 76, 74, 78, and 72 are formed to expose the lower layers 201 and 601, respectively. Also in this case, the contact holes 76, 74, 78, and 72 of the drain electrode 66, the gate pad 24, the data pad 68, and the conductive capacitor 64 for the storage capacitor are the same as in the first embodiment. At least one branch of the drain electrode 66, the gate pad 24, the data pad 68, and the conductive capacitor conductor 64 for the storage capacitor is formed to expose all the boundary lines of the lower layers 201 and 601. It is formed so as to be covered by 70. This is to maximize the contact area having a low contact resistance at the contact as described in the first embodiment and to minimize the contact resistance with the driving integrated circuit.
    [104] Finally, as shown in Figs. 11 to 13, the IZO layer having a thickness of 400 mV to 500 mV is deposited by the sputtering method in the same manner as in the first embodiment, and is etched using a fourth mask to etch the drain electrode 66. And a pixel electrode 82 connected to the conductive capacitor 64 for the storage capacitor, an auxiliary gate pad 84 connected to the gate pad 24, and an auxiliary data pad 88 connected to the data pad 68. The etchant for patterning IZO uses chromium etchant which is used to etch the metal film of chromium (Cr), which does not corrode aluminum and thus prevents corrosion of data wiring or gate wiring, and the etching solution (HNO 3 / (NH 4 ) 2 Ce (NO 3 ) 6 / H 2 O), and the like.
    [105] In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48) may be formed using one mask, and the source electrode 65 and the drain electrode 66 may be separated in this process to simplify the manufacturing process.
    [106] As described above, according to the present invention, the wiring is formed to have a protrusion or a branch, and the IZO film and the conductive film having a low contact resistance are formed to maximize the area having a low contact resistance, thereby ensuring the reliability of the contact portion. In addition, at least one protrusion or branch may be formed in the contact portion to the lower portion of the protective film to prevent the IZO film from disconnecting at the contact portion. In addition, by forming a wiring including a conductive film containing low resistance aluminum or an aluminum alloy, the characteristics of a large screen high definition product can be improved. In addition, the manufacturing process may be simplified to manufacture a thin film transistor substrate for a liquid crystal display, thereby simplifying the manufacturing process and reducing the manufacturing cost.
    权利要求:
    Claims (9)
    [1" claim-type="Currently amended] A wiring formed on the substrate and having branches or protrusions,
    A portion of the boundary line exposing the wiring line has a contact hole located outside the boundary line of the wiring line, and a portion of the boundary line of the contact hole is an insulating film positioned above the branch or protrusion of at least one of the wiring lines,
    A conductive layer formed of IZO on the insulating film and in contact with the wiring through the contact hole.
    Contact structure of the wiring comprising a.
    [2" claim-type="Currently amended] In claim 1,
    The wiring is a contact structure of a wiring comprising a lower film of chromium or molybdenum or molybdenum alloy and an aluminum or aluminum alloy and an upper film formed inside the boundary of the lower film.
    [3" claim-type="Currently amended] A gate line formed on an insulating substrate and extending in a horizontal direction, the gate line including a gate electrode connected to the gate line,
    A gate insulating film covering the gate wiring,
    A semiconductor layer formed on the gate insulating film,
    A data line formed on the semiconductor layer or the gate insulating layer, the data line extending in a vertical direction crossing the gate line, a source electrode connected to the data line, and separated from the source electrode, the source electrode being centered on the gate electrode; A data wiring comprising a drain electrode facing and having a branch or a protrusion,
    A passivation layer covering the data line and the semiconductor layer and having a first contact hole exposing a boundary line of the drain electrode, wherein the boundary line passing through the first contact hole passes through at least one branch or protrusion;
    A pixel electrode formed on the passivation layer and connected to the drain electrode through the first contact hole;
    Thin film transistor substrate comprising a.
    [4" claim-type="Currently amended] In claim 3,
    The gate wiring or the data wiring is formed inside a boundary between the lower layer of the chromium, molybdenum or molybdenum alloy and the lower layer, and includes a top layer of aluminum or an aluminum alloy.
    [5" claim-type="Currently amended] In claim 3,
    The thin film transistor substrate of which the gate insulating film and the protective film are made of silicon nitride.
    [6" claim-type="Currently amended] In claim 3,
    The pixel electrode is a thin film transistor substrate made of IZO.
    [7" claim-type="Currently amended] In claim 3,
    The gate line receives a scan signal from the outside and transfers the scan signal to the gate line, and includes a gate pad having a branch or a protrusion.
    The data line may include a data pad having a branch or a protrusion and transferring the data line to the data line to receive an image signal from the outside.
    The passivation layer has a second contact hole for exposing the gate pad or the data pad, and the thin film transistor substrate is disposed on the branch or protrusion of the at least one branch bordering the second contact hole.
    [8" claim-type="Currently amended] In claim 7,
    Sidewalls of the drain electrode and the data pad or the gate pad are exposed in the first or second contact hole, and the pixel electrode and the auxiliary data pad or the auxiliary data pad are at least the drain electrode and the data pad or the gate pad. A thin film transistor substrate in contact with the sidewalls of the thin film transistor substrate.
    [9" claim-type="Currently amended] In claim 3,
    The semiconductor layer except for the channel portion between the source and drain electrodes, the data wiring is formed in the same shape.
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    同族专利:
    公开号 | 公开日
    KR100796757B1|2008-01-22|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-11-29|Application filed by 삼성전자주식회사
    2001-11-29|Priority to KR1020010074897A
    2003-06-09|Publication of KR20030044217A
    2008-01-22|Application granted
    2008-01-22|Publication of KR100796757B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020010074897A|KR100796757B1|2001-11-29|2001-11-29|A contact structure of a wires, and thin film transistor substrate including the contact structure|
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